`timescale 1ns / 1ps
/******************************************************************************
*                                                                             *
* UTICA softcore v0.1                                                         *
*                                                                             *
* Copyright (c) 2012 Andrew D. Zonenberg                                      *
* All rights reserved.                                                        *
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* Redistribution and use in source and binary forms, with or without modifi-  *
* cation, are permitted provided that the following conditions are met:       *
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*    * Neither the name of the author nor the names of any contributors may be*
*      used to endorse or promote products derived from this software without *
*      specific prior written permission.                                     *
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******************************************************************************/

/**
	@file NullPacketSink.v
	@author Andrew D. Zonenberg
	@brief Discards all packets we get.
 */
module NullPacketSink(
	clk,
	packet_ready, read_word, rx_data, rx_rdy, read_done
    );
	 
	////////////////////////////////////////////////////////////////////////////////////////////////
	// IO declarations

	input wire clk;

	input wire packet_ready;			//Asserted by the Ethernet interface for one clock when it
												//receives a packet with our designated ethertype value.
	output reg read_word = 0;			//Request another word of the packet
	input wire[15:0] rx_data;			//Next word of the packet
												//If packet_ready is asserted it's instead the length of
												//the layer 3 packet including headers and padding
	input wire rx_rdy;					//Indicates the data being read is valid
	output reg read_done = 0;			//Indicates we're done reading the packet/
												//All remaining data in the packet, if any, is discarded.

	////////////////////////////////////////////////////////////////////////////////////////////////
	// Control code
	
	//When a packet gets here, discard it	
	always @(posedge clk) begin
		read_done <= 0;
		if(packet_ready)
			read_done <= 1;
	end

endmodule
